Madiel de Souza Conserva Filho / bts

Cell3_saida_1.38689112926E12.log 617 Bytes
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Checking cspFiles/Cell3.csp

Checking Test(inter(inputs(Cell3),outputs(Cell3)) == {}) [T= ERROR
xtrue
BEGIN TRACE example=0 process=1
error
END TRACE example=0 process=1

Checking HideAll(Cell3) :[divergence free [FD]]
xtrue
BEGIN TRACE example=0 process=0

END TRACE example=0 process=0

Checking Cell3 :[divergence free [FD]]
true

Checking LHS_InputDet(Cell3) [F= RHS_InputDet(Cell3)
true

Checking LHS_OutputDec_A(Cell3) [F= RHS_OutputDec_A(Cell3)
true

Checking LHS_OutputDec_B(Cell3,rd_i.3) [F= RHS_OutputDec_B(Cell3,rd_i.3)
true

Checking LHS_OutputDec_B(Cell3,wrt_i.3) [F= RHS_OutputDec_B(Cell3,wrt_i.3)
true