Cell2_saida_1.386941704466E12.log 617 Bytes
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Checking cspFiles/Cell2.csp

Checking Test(inter(inputs(Cell2),outputs(Cell2)) == {}) [T= ERROR
xtrue
BEGIN TRACE example=0 process=1
error
END TRACE example=0 process=1

Checking HideAll(Cell2) :[divergence free [FD]]
xtrue
BEGIN TRACE example=0 process=0

END TRACE example=0 process=0

Checking Cell2 :[divergence free [FD]]
true

Checking LHS_InputDet(Cell2) [F= RHS_InputDet(Cell2)
true

Checking LHS_OutputDec_A(Cell2) [F= RHS_OutputDec_A(Cell2)
true

Checking LHS_OutputDec_B(Cell2,rd_i.2) [F= RHS_OutputDec_B(Cell2,rd_i.2)
true

Checking LHS_OutputDec_B(Cell2,wrt_i.2) [F= RHS_OutputDec_B(Cell2,wrt_i.2)
true