Madiel de Souza Conserva Filho / bts

Controller1.csp~ 3.38 KB
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include "sequence_aux.csp" 
include "function_aux.csp" 
include "auxiliar.csp" 
include "rules.csp"


datatype Direction = req | ack
Value = {1..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel rd_i : CellId.Direction.Value
channel wrt_i : CellId.Direction.Value


Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell
maxbuff = 4

maxring = maxbuff - 1

Controller =
 let ControllerState(cache,size,top,bot) =
       InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot)

     InputController(cache,size,top,bot) =
       size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot)
                                    []
                                    size > 0 & write.top.req!x -> write.top.ack?dumb ->  ControllerState(cache,size+1,(top%maxring)+1,bot))

     OutputController(cache,size,top,bot) =
       size > 0 & output!cache -> (size > 1 &
-- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive
--                                        read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)
                                        (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1))
                                   []
                                   size == 1 & ControllerState(cache,0,top,bot))

 within
 --  The initial value of the cache is irrelevant, since the size is 0.
   ControllerState(0,0,1,1)



RenameContract(i) = Controller [[input <- input,output <- output,write <- write.1,read <- read.1]] 
Inst_Controller1 = <(input,input),(output,output),(write,write.1),(read,read.1)> 
Controller1 = rename(Controller, Inst_Controller1) 


GET_CHANNELS(P) =
 	 let f =
 	 < 
 	 (Controller1, { 
input,output,write.1,read.1 }) 
 	 > 

 	 within apply(f,P )

inputs(P) = 
 	 let f = 

 	 < 
 ( Controller1, {| input, write.1.1.ack, write.1.2.ack, write.1.3.ack, read.1.1.ack, read.1.2.ack, read.1.3.ack |}) 
 	 > 

 	 within apply(f, P )

outputs(P) = 
 	 let f =
 	 < 
 ( Controller1, {| output, write.1.1.req, write.1.2.req, write.1.3.req, read.1.1.req, read.1.2.req, read.1.3.req |}) 
 	 >
 	 within apply(f,P)

--Condition A.1: Alphabets are disjont
--assert STOP [T= RUN(inter(events(Controller1),events(Controller1)))

--Condition A.2: I/O Process
--Condition A.2.1: Every channel in P is an I/O Channel
assert not Test(inter(inputs(Controller1),outputs(Controller1)) == {}) [T= ERROR

--Condition A.2.2: The contract has infinite set of traces
assert not HideAll(Controller1):[divergence free [FD]]

--Condition A.2.3: The contract is divergence-free
assert Controller1:[divergence free [FD]]

--Condition A.2.4: The contract is input deterministic
assert LHS_InputDet(Controller1) [F= RHS_InputDet(Controller1)

--Condition A.2.5: The contract is strong output decisive
assert LHS_OutputDec_A(Controller1) [F= RHS_OutputDec_A(Controller1)
assert LHS_OutputDec_B(Controller1,input) [F= RHS_OutputDec_B(Controller1,input)
assert LHS_OutputDec_B(Controller1,output) [F= RHS_OutputDec_B(Controller1,output)
assert LHS_OutputDec_B(Controller1,write.1) [F= RHS_OutputDec_B(Controller1,write.1)
assert LHS_OutputDec_B(Controller1,read.1) [F= RHS_OutputDec_B(Controller1,read.1)