Madiel de Souza Conserva Filho / bts

Controller.csp 3.03 KB
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include "sequence_aux.csp" 
include "function_aux.csp" 
include "auxiliar.csp" 
include "rules.csp"

datatype Direction = req | ack
Value = {0..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel wrt_i : CellId.Direction.Value
channel rd_i : CellId.Direction.Value

maxbuff = 4

maxring = maxbuff - 1

Controller =
 let ControllerState(cache,size,top,bot) =
       InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot)

     InputController(cache,size,top,bot) =
       size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot)
                                    []
                                    size > 0 & write.top.req!x -> write.top.ack?dumb ->  ControllerState(cache,size+1,(top%maxring)+1,bot))

     OutputController(cache,size,top,bot) =
       size > 0 & output!cache -> (size > 1 &
-- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive
--                                        read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)
                                        (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1))
                                   []
                                   size == 1 & ControllerState(cache,0,top,bot))

 within
 --  The initial value of the cache is irrelevant, since the size is 0.
   ControllerState(0,0,1,1)


GET_CHANNELS(P) =
 	 let f =
 	 < 
 	(Controller, { input,output,write,read }) 
 	 > 

 	 within apply(f,P )

inputs(P) = 
 	 let f = 

 	 < 
 	 ( Controller, {| input, write.1.ack, write.2.ack, write.3.ack, read.1.ack, read.2.ack, read.3.ack |}) 
 	 > 

 	 within apply(f, P )

outputs(P) = 
 	 let f =
 	 < 
 	 ( Controller, {| output, write.1.req, write.2.req, write.3.req, read.1.req, read.2.req, read.3.req |}) 
 	 >
 	 within apply(f,P)

--Condition A.1: Alphabets are disjont
--assert STOP [T= RUN(inter(events(Controller),events(Controller)))

--Condition A.2: I/O Process
--Condition A.2.1: Every channel in P is an I/O Channel
assert not Test(inter(inputs(Controller),outputs(Controller)) == {}) [T= ERROR

--Condition A.2.2: The contract has infinite set of traces
assert not HideAll(Controller):[divergence free [FD]]

--Condition A.2.3: The contract is divergence-free
assert Controller:[divergence free [FD]]

--Condition A.2.4: The contract is input deterministic
assert LHS_InputDet(Controller) [F= RHS_InputDet(Controller)

--Condition A.2.5: The contract is strong output decisive
assert LHS_OutputDec_A(Controller) [F= RHS_OutputDec_A(Controller)
assert LHS_OutputDec_B(Controller,input) [F= RHS_OutputDec_B(Controller,input)
assert LHS_OutputDec_B(Controller,output) [F= RHS_OutputDec_B(Controller,output)
assert LHS_OutputDec_B(Controller,write) [F= RHS_OutputDec_B(Controller,write)
assert LHS_OutputDec_B(Controller,read) [F= RHS_OutputDec_B(Controller,read)