Madiel de Souza Conserva Filho / bts

Cell2.csp 2.95 KB
edit raw blame history 
   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
include "sequence_aux.csp" 
include "function_aux.csp" 
include "auxiliar.csp" 
include "rules.csp"


datatype Direction = req | ack
Value = {0..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel wrt_i : CellId.Direction.Value
channel rd_i : CellId.Direction.Value


Cell = 
  let CellState(val) =
    rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x)
  within
    CellState(0)
maxbuff = 4

maxring = maxbuff - 1

Controller =
 let ControllerState(cache,size,top,bot) =
       InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot)

     InputController(cache,size,top,bot) =
       size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot)
                                    []
                                    size > 0 & write.top.req!x -> write.top.ack?dumb ->  ControllerState(cache,size+1,(top%maxring)+1,bot))

     OutputController(cache,size,top,bot) =
       size > 0 & output!cache -> (size > 1 &
-- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive
--                                        read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)
                                        (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1))
                                   []
                                   size == 1 & ControllerState(cache,0,top,bot))

 within
 --  The initial value of the cache is irrelevant, since the size is 0.
   ControllerState(0,0,1,1)



RenameContract(i) = Cell [[rd <- rd_i.2,wrt <- wrt_i.2]] 
Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> 
Cell2 = rename(Cell, Inst_Cell2) 


GET_CHANNELS(P) =
 	 let f =
 	 < 
 	 (Cell2, { 
rd_i.2,wrt_i.2 }) 
 	 > 

 	 within apply(f,P )

inputs(P) = 
 	 let f = 

 	 < 
 ( Cell2, {| rd_i.2.req, wrt_i.2.req |}) 
 	 > 

 	 within apply(f, P )

outputs(P) = 
 	 let f =
 	 < 
 ( Cell2, {| rd_i.2.ack, wrt_i.2.ack |}) 
 	 >
 	 within apply(f,P)

--Condition A.1: Alphabets are disjont
--assert STOP [T= RUN(inter(events(Cell2),events(Cell2)))

--Condition A.2: I/O Process
--Condition A.2.1: Every channel in P is an I/O Channel
assert not Test(inter(inputs(Cell2),outputs(Cell2)) == {}) [T= ERROR

--Condition A.2.2: The contract has infinite set of traces
assert not HideAll(Cell2):[divergence free [FD]]

--Condition A.2.3: The contract is divergence-free
assert Cell2:[divergence free [FD]]

--Condition A.2.4: The contract is input deterministic
assert LHS_InputDet(Cell2) [F= RHS_InputDet(Cell2)

--Condition A.2.5: The contract is strong output decisive
assert LHS_OutputDec_A(Cell2) [F= RHS_OutputDec_A(Cell2)
assert LHS_OutputDec_B(Cell2,rd_i.2) [F= RHS_OutputDec_B(Cell2,rd_i.2)
assert LHS_OutputDec_B(Cell2,wrt_i.2) [F= RHS_OutputDec_B(Cell2,wrt_i.2)