include "sequence_aux.csp" 
include "function_aux.csp" 
include "auxiliar.csp" 
include "rules.csp"

datatype Direction = req | ack
Value = {1..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel rd_i : CellId.Direction.Value
channel wrt_i : CellId.Direction.Value

BricRingCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> BricRingCell


GET_CHANNELS(P) =
 	 let f =
 	 < 
 	(BricRingCell, { rd,wrt }) 
 	 > 

 	 within apply(f,P )

inputs(P) = 
 	 let f = 

 	 < 
 	 ( BricRingCell, {| rd.req, wrt.req |}) 
 	 > 

 	 within apply(f, P )

outputs(P) = 
 	 let f =
 	 < 
 	 ( BricRingCell, {| rd.ack, wrt.ack |}) 
 	 >
 	 within apply(f,P)

--Condition A.1: Alphabets are disjont
--assert STOP [T= RUN(inter(events(BricRingCell),events(BricRingCell)))

--Condition A.2: I/O Process
--Condition A.2.1: Every channel in P is an I/O Channel
assert not Test(inter(inputs(BricRingCell),outputs(BricRingCell)) == {}) [T= ERROR

--Condition A.2.2: The contract has infinite set of traces
assert not HideAll(BricRingCell):[divergence free [FD]]

--Condition A.2.3: The contract is divergence-free
assert BricRingCell:[divergence free [FD]]

--Condition A.2.4: The contract is input deterministic
assert LHS_InputDet(BricRingCell) [F= RHS_InputDet(BricRingCell)

--Condition A.2.5: The contract is strong output decisive
assert LHS_OutputDec_A(BricRingCell) [F= RHS_OutputDec_A(BricRingCell)
assert LHS_OutputDec_B(BricRingCell,rd) [F= RHS_OutputDec_B(BricRingCell,rd)
assert LHS_OutputDec_B(BricRingCell,wrt) [F= RHS_OutputDec_B(BricRingCell,wrt)