Checking fdrLog/BUF0.csp

Checking Test(inter(inputs(BUF0),outputs(BUF0)) == {}) [T= ERROR
xtrue
BEGIN TRACE example=0 process=1
error
END TRACE example=0 process=1

Checking HideAll(BUF0) :[divergence free [FD]]
xtrue
BEGIN TRACE example=0 process=0

END TRACE example=0 process=0

Checking BUF0 :[divergence free [FD]]
true

Checking LHS_InputDet(BUF0) [F= RHS_InputDet(BUF0)
true

Checking LHS_OutputDec_A(BUF0) [F= RHS_OutputDec_A(BUF0)
true

Checking LHS_OutputDec_B(BUF0,write0) [F= RHS_OutputDec_B(BUF0,write0)
true

Checking LHS_OutputDec_B(BUF0,read0) [F= RHS_OutputDec_B(BUF0,read0)
true