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BRIC/fdrLog/Controllerr_saida_1.386882859036E12.log 867 Bytes
eeb5cac08   Madiel de Souza Conserva Filho   first
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  Checking cspFiles/Controllerr.csp
  
  Checking Test(inter(inputs(Controllerr),outputs(Controllerr)) == {}) [T= ERROR
  xtrue
  BEGIN TRACE example=0 process=1
  error
  END TRACE example=0 process=1
  
  Checking HideAll(Controllerr) :[divergence free [FD]]
  xtrue
  BEGIN TRACE example=0 process=0
  
  END TRACE example=0 process=0
  
  Checking Controllerr :[divergence free [FD]]
  true
  
  Checking LHS_InputDet(Controllerr) [F= RHS_InputDet(Controllerr)
  true
  
  Checking LHS_OutputDec_A(Controllerr) [F= RHS_OutputDec_A(Controllerr)
  true
  
  Checking LHS_OutputDec_B(Controllerr,input) [F= RHS_OutputDec_B(Controllerr,input)
  true
  
  Checking LHS_OutputDec_B(Controllerr,output) [F= RHS_OutputDec_B(Controllerr,output)
  true
  
  Checking LHS_OutputDec_B(Controllerr,write) [F= RHS_OutputDec_B(Controllerr,write)
  true
  
  Checking LHS_OutputDec_B(Controllerr,read) [F= RHS_OutputDec_B(Controllerr,read)
  true