ysrjava.util.LinkedList )S]J`"xpw srLOGIC.ObjectSaved^ςtLnometLjava/lang/String;LsavetLLOGIC/ObjectList;xptcanaissrLOGIC.ObjectListժ7 IdefaultrenameNumberL channelListtLjava/util/List;L contractListq~L instanceListq~LprocessosAuxiliaresq~LtypeListq~xpsq~wsr LOGIC.Channelp^9M0FLflagq~Lnameq~Ltypeq~xpptrdsq~wsrLOGIC.DatatypelT\\Ldatatypeq~xr LOGIC.Type [KLnomeq~Ltipoq~xpt Directiontdatatypesq~wsrLOGIC.DatatypeElementEoЯ Lnameq~Ltypeq~xptreqtsq~tackq~xsrLOGIC.IntervalType;ImaxImimxq~tValuet intervaloxsq~ ptwrtsq~wq~q~xsq~ ptwritesq~wsq~tCellIdq~q~q~xsq~ ptreadsq~wq~%q~q~xsq~ ptinputsq~wq~xsq~ ptoutputsq~wq~xsq~ ptwrt_isq~wq~%q~q~xsq~ ptrd_isq~wq~%q~q~xxsq~wxsq~wxq~sq~wq~q~q~%xsq~tcellsq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~Gxsq~tValuet intervaloxsq~ q~>twrtsq~wq~Aq~Jxsq~ ptwritesq~wsq~tCellIdq~Lq~Aq~Jxsq~ ptreadsq~wq~Sq~Aq~Jxsq~ ptinputsq~wq~Jxsq~ ptoutputsq~wq~Jxsq~ tcctwrt_isq~wq~Sq~Aq~Jxsq~ q~_trd_isq~wq~Sq~Aq~Jxxsq~wsrLOGIC.Contract"~dO ZflagLbehaviorq~Lchannelq~Leventsq~Linq~Lnameq~Loutq~L protocolostLjava/util/LinkedList;Ltypeq~xpt@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~Mq~=q~^q~bxsq~wsrLOGIC.EventChannel wǢ?LchanneltLLOGIC/Channel;Leventoq~Lsufixoq~xpq~^twrt_i.2t.2sq~lq~^twrt_i.3t.3sq~lq~btrd_i.1t.1sq~lq~btrd_i.2t.2sq~lq~btrd_i.3t.3xsq~wsq~lq~Mtwrt.reqt.reqsq~lq~=trd.reqt.reqxtCellsq~wsq~lq~Mtwrt.ackt.acksq~lq~=trd.ackt.ackxsq~wsrLOGIC.ProtocolsxgLcChannelq~Lcanalq~mL dualProtocolq~Lprotocolq~xptwrt_i.1q~^tq~sq~twrt_i.2q~^tq~sq~twrt_i.3q~^q~q~sq~trd_i.1q~bq~q~sq~trd_i.2q~bq~q~sq~trd_i.3q~bq~q~xsq~wxxsq~wxq~Gsq~wq~Aq~Jq~Sxsq~tContractControllerOKsq~sq~wsq~ tcctrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~xsq~ q~twritesq~wsq~tCellIdq~q~q~xsq~ q~treadsq~wq~q~q~xsq~ tintinputsq~wq~xsq~ touttoutputsq~wq~xsq~ ptwrt_isq~wq~q~q~xsq~ ptrd_isq~wq~q~q~xxsq~wsq~ft@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~q~xsq~wxsq~wsq~lq~trd.reqt.reqsq~lq~twrt.reqt.reqxtCellsq~wsq~lq~trd.ackt.acksq~lq~twrt.ackt.ackxsq~wsq~trdq~tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) sq~wq~q~q~q~xsq~wsq~lq~twrite.1t.1sq~lq~twrite.2t.2sq~lq~twrite.3t.3sq~lq~tread.1t.1sq~lq~tread.2t.2sq~lq~tread.3t.3sq~lq~tinputtsq~lq~toutputq~sq~lq~t write.1.ackt.1.acksq~lq~t write.2.ackt.2.acksq~lq~t write.3.ackt.3.acksq~lq~t read.1.ackt.1.acksq~lq~t read.2.ackt.2.acksq~lq~t read.3.ackt.3.acksq~lq~t write.1.reqt.1.reqsq~lq~t write.2.reqt.2.reqsq~lq~t write.3.reqt.3.reqsq~lq~t read.1.reqt.1.reqsq~lq~t read.2.reqt.2.reqsq~lq~t read.3.reqt.3.reqxsq~wq~q~q~q~ q~q~q~xt Controllersq~wq~q~q~q~q~ q~#q~&xsq~wsq~twrite.1q~q~q~sq~twrite.2q~q~q~sq~twrite.3q~q~q~sq~tread.1q~q~q~sq~tread.2q~q~q~sq~tread.3q~q~q~xsq~wxxsq~wxt PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e)sq~wq~q~q~xsq~t instanceOKsq~sq~wsq~ tcctrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~Kxsq~tValuet intervaloxsq~ q~Btwrtsq~wq~Eq~Nxsq~ q~Btwritesq~wsq~tCellIdq~Pq~Eq~Nxsq~ q~Btreadsq~wq~Wq~Eq~Nxsq~ tintinputsq~wq~Nxsq~ touttoutputsq~wq~Nxsq~ ptwrt_isq~wq~Wq~Eq~Nxsq~ ptrd_isq~wq~Wq~Eq~Nxxsq~wsq~ft@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~Aq~Qxsq~wxsq~wsq~lq~Atrd.reqt.reqsq~lq~Qtwrt.reqt.reqxtCellsq~wsq~lq~Atrd.ackt.acksq~lq~Qtwrt.ackt.ackxsq~wsq~trdq~AtDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~QtDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) sq~wq~Tq~Yq~\q~`xsq~wxsq~wsq~lq~\tinputtsq~lq~Tt write.1.ackt.1.acksq~lq~Tt write.2.ackt.2.acksq~lq~Tt write.3.ackt.3.acksq~lq~Yt read.1.ackt.1.acksq~lq~Yt read.2.ackt.2.acksq~lq~Yt read.3.ackt.3.ackxt Controllersq~wsq~lq~`toutputq~sq~lq~Tt write.1.reqt.1.reqsq~lq~Tt write.2.reqt.2.reqsq~lq~Tt write.3.reqt.3.reqsq~lq~Yt read.1.reqt.1.reqsq~lq~Yt read.2.reqt.2.reqsq~lq~Yt read.3.reqt.3.reqxsq~wsq~twrite.1q~TtDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~TtDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~TtDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~YtDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~YtDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~YtDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wsrLOGIC.InstanceGZfGcLcontratotLLOGIC/Contract;xq~fq~lsq~wsq~ ptrd_i.1q~Dsq~ ptwrt_i.1q~Sxsq~wxsq~wsq~lsq~ q~Bq~q~Dt rd_i.1.reqq~rsq~lsq~ q~Bq~q~St wrt_i.1.reqq~uxtCell1sq~wsq~lq~t rd_i.1.ackq~zsq~lq~t wrt_i.1.ackq~}xsq~wsq~trd_i.1q~tDUAL_PROT_CELL(rd_i.1)tPROT_CELL(rd_i.1)sq~twrt_i.1q~tDUAL_PROT_CELL(wrt_i.1)tPROT_CELL(wrt_i.1)xq~q~ksq~q~lsq~wsq~ ptrd_i.2q~Dsq~ ptwrt_i.2q~Sxsq~wxsq~wsq~lsq~ q~Bq~q~Dt rd_i.2.reqq~rsq~lsq~ q~Bq~q~St wrt_i.2.reqq~uxtCell2sq~wsq~lq~t rd_i.2.ackq~zsq~lq~t wrt_i.2.ackq~}xsq~wsq~trd_i.2q~tDUAL_PROT_CELL(rd_i.2)tPROT_CELL(rd_i.2)sq~twrt_i.2q~tDUAL_PROT_CELL(wrt_i.2)tPROT_CELL(wrt_i.2)xq~q~ksq~q~lsq~wsq~ ptrd_i.3q~Dsq~ ptwrt_i.3q~Sxsq~wxsq~wsq~lsq~ q~Bq~q~Dt rd_i.3.reqq~rsq~lsq~ q~Bq~q~St wrt_i.3.reqq~uxtCell3sq~wsq~lq~t rd_i.3.ackq~zsq~lq~t wrt_i.3.ackq~}xsq~wsq~trd_i.3q~tDUAL_PROT_CELL(rd_i.3)tPROT_CELL(rd_i.3)sq~twrt_i.3q~tDUAL_PROT_CELL(wrt_i.3)tPROT_CELL(wrt_i.3)xq~q~ksq~q~sq~wsq~ ptwriteq~Vsq~ ptreadq~[sq~ ptinputq~_sq~ ptoutputq~cxsq~wxsq~wsq~lsq~ q~]q~3q~_tinputq~sq~lsq~ q~Bq~/q~Vt write.1.ackq~sq~lq~ e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e)sq~wq~Eq~Nq~Wxsq~tcomposicao_intersq~sq~wsq~ tcctrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~ztwrtsq~wq~}q~xsq~ q~ztwritesq~wsq~tCellIdq~q~}q~xsq~ q~ztreadsq~wq~q~}q~xsq~ tintinputsq~wq~xsq~ touttoutputsq~wq~xsq~ ptwrt_isq~wq~q~}q~xsq~ ptrd_isq~wq~q~}q~xxsq~wsq~ft@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~yq~xsq~wxsq~wsq~lq~ytrd.reqt.reqsq~lq~twrt.reqt.reqxtCellsq~wsq~lq~ytrd.ackt.acksq~lq~twrt.ackt.ackxsq~wsq~trdq~ytDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) sq~wq~q~q~q~xsq~wxsq~wsq~lq~tinputtsq~lq~t write.1.ackt.1.acksq~lq~t write.2.ackt.2.acksq~lq~t write.3.ackt.3.acksq~lq~t read.1.ackt.1.acksq~lq~t read.2.ackt.2.acksq~lq~t read.3.ackt.3.ackxt Controllersq~wsq~lq~toutputq~sq~lq~t write.1.reqt.1.reqsq~lq~t write.2.reqt.2.reqsq~lq~t write.3.reqt.3.reqsq~lq~t read.1.reqt.1.reqsq~lq~t read.2.reqt.2.reqsq~lq~t read.3.reqt.3.reqxsq~wsq~twrite.1q~tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wsq~q~sq~wsq~ ptwriteq~sq~ ptreadq~sq~ ptinputq~sq~ ptoutputq~xsq~wxsq~wsq~lsq~ q~q~q~tinputq~sq~lsq~ q~zq~q~t write.1.ackq~sq~lq~t write.2.ackq~sq~lq~t write.3.ackq~sq~lsq~ q~zq~q~t read.1.ackq~sq~lq~"t read.2.ackq~sq~lq~"t read.3.ackq~xt Controller3sq~wsq~lsq~ q~q~q~toutputq~sq~lq~t write.1.reqq~sq~lq~t write.2.reqq~sq~lq~t write.3.reqq~sq~lq~"t read.1.reqq~sq~lq~"t read.2.reqq~sq~lq~"t read.3.reqq~xsq~wsq~twrite.1q~ tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~ tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~ tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xq~ q~srLOGIC.ComponenteLÆ1L instance1tLLOGIC/Instance;L instance2q~Sxq~tsq~wsq~ ptrd_i.1q~|sq~ ptwrt_i.1q~sq~ ptrd_i.2q~|sq~ ptwrt_i.2q~sq~ ptrd_i.3q~|sq~ ptwrt_i.3q~xsq~wxsq~wsq~lsq~ q~zq~Xq~|t rd_i.1.reqq~sq~lsq~ q~zq~Zq~t wrt_i.1.reqq~sq~lsq~ q~zq~\q~|t rd_i.2.reqq~sq~lsq~ q~zq~^q~t wrt_i.2.reqq~sq~lsq~ q~zq~`q~|t rd_i.3.reqq~sq~lsq~ q~zq~bq~t wrt_i.3.reqq~xtCell1_Cell2_INTER_Cell3_INTERsq~wsq~lq~ft rd_i.1.ackq~sq~lq~it wrt_i.1.ackq~sq~lq~lt rd_i.2.ackq~sq~lq~ot wrt_i.2.ackq~sq~lq~rt rd_i.3.ackq~sq~lq~ut wrt_i.3.ackq~xsq~wsq~trd_i.1q~WtDUAL_PROT_CELL(rd_i.1)tPROT_CELL(rd_i.1)sq~twrt_i.1q~YtDUAL_PROT_CELL(wrt_i.1)tPROT_CELL(wrt_i.1)sq~trd_i.2q~[tDUAL_PROT_CELL(rd_i.2)tPROT_CELL(rd_i.2)sq~twrt_i.2q~]tDUAL_PROT_CELL(wrt_i.2)tPROT_CELL(wrt_i.2)sq~trd_i.3q~_tDUAL_PROT_CELL(rd_i.3)tPROT_CELL(rd_i.3)sq~twrt_i.3q~atDUAL_PROT_CELL(wrt_i.3)tPROT_CELL(wrt_i.3)xsq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell Cell1_Cell2 = INTER(Cell1, Cell2) Inst_Cell1 = <(rd,rd_i.1),(wrt,wrt_i.1)> Cell1 = rename(Cell, Inst_Cell1) Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> Cell2 = rename(Cell, Inst_Cell2) Cell1_Cell2_INTER_Cell3 = INTER(Cell1_Cell2_INTER, Cell3) Inst_Cell1_Cell2_INTER = <(rd,rd_i.1),(wrt,wrt_i.1),(rd,rd_i.2),(wrt,wrt_i.2)> Cell1_Cell2_INTER = rename(Cell1_Cell2, Inst_Cell1_Cell2_INTER) Inst_Cell3 = <(rd,rd_i.3),(wrt,wrt_i.3)> Cell3 = rename(Cell, Inst_Cell3) sq~wq~yq~q~yq~q~yq~xsq~wxsq~wxtCell1_Cell2_INTER_Cell3sq~wxsq~wxsq~wxsq~Rq~Usq~wq~Wq~Yq~[q~]xsq~wxsq~wq~eq~hq~kq~nxtCell1_Cell2_INTERsq~wq~yq~{q~}q~xq~sq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell Cell1_Cell2 = INTER(Cell1, Cell2) Inst_Cell1 = <(rd,rd_i.1),(wrt,wrt_i.1)> Cell1 = rename(Cell, Inst_Cell1) Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> Cell2 = rename(Cell, Inst_Cell2) sq~wq~yq~q~yq~xsq~wxsq~wxt Cell1_Cell2sq~wxsq~wxsq~wxsq~q~sq~wq~Wq~Yxsq~wxsq~wq~eq~hxtCell1sq~wq~yq~{xq~q~q~sq~q~sq~wq~[q~]xsq~wxsq~wq~kq~nxtCell2sq~wq~}q~xsq~wq~q~xq~q~sq~q~sq~wq~_q~axsq~wxsq~wq~qq~txtCell3sq~wq~q~xsq~wq~q~xq~q~xt PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e)sq~wq~}q~q~xsq~tcomposicao_commsq~sq~wsq~ tcctrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~xsq~ q~twritesq~wsq~tCellIdq~q~q~xsq~ q~treadsq~wq~q~q~xsq~ tintinputsq~wq~xsq~ touttoutputsq~wq~xsq~ ptwrt_isq~wq~q~q~xsq~ ptrd_isq~wq~q~q~xxsq~wsq~ft@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~q~xsq~wxsq~wsq~lq~trd.reqt.reqsq~lq~twrt.reqt.reqxtCellsq~wsq~lq~trd.ackt.acksq~lq~twrt.ackt.ackxsq~wsq~trdq~tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) sq~wq~q~q~q~xsq~wxsq~wsq~lq~tinputtsq~lq~t write.1.ackt.1.acksq~lq~t write.2.ackt.2.acksq~lq~t write.3.ackt.3.acksq~lq~t read.1.ackt.1.acksq~lq~t read.2.ackt.2.acksq~lq~t read.3.ackt.3.ackxt Controllersq~wsq~lq~toutputq~ sq~lq~t write.1.reqt.1.reqsq~lq~t write.2.reqt.2.reqsq~lq~t write.3.reqt.3.reqsq~lq~t read.1.reqt.1.reqsq~lq~t read.2.reqt.2.reqsq~lq~t read.3.reqt.3.reqxsq~wsq~twrite.1q~tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wsq~Rtsq~w sq~ ptrd_i.1q~sq~ ptwrt_i.1q~sq~ ptrd_i.2q~sq~ ptwrt_i.2q~sq~ ptrd_i.3q~sq~ ptwrt_i.3q~sq~ ptwriteq~sq~ ptreadq~sq~ ptinputq~sq~ ptoutputq~xsq~wxsq~w sq~lsq~ q~q~hq~t rd_i.1.reqq~sq~lsq~ q~q~jq~t wrt_i.1.reqq~sq~lsq~ q~q~lq~t rd_i.2.reqq~sq~lsq~ q~q~nq~t wrt_i.2.reqq~sq~lsq~ q~q~pq~t rd_i.3.reqq~sq~lsq~ q~q~rq~t wrt_i.3.reqq~sq~lsq~ q~q~xq~tinputq~ sq~lsq~ q~q~tq~t write.1.ackq~#sq~lq~t write.2.ackq~&sq~lq~t write.3.ackq~)sq~lsq~ q~q~vq~t read.1.ackq~,sq~lq~t read.2.ackq~/sq~lq~t read.3.ackq~2xt.Cell1_Cell2_INTER_Cell3_INTER_Controller3_COMMsq~w sq~lq~~t rd_i.1.ackq~ sq~lq~t wrt_i.1.ackq~sq~lq~t rd_i.2.ackq~ sq~lq~t wrt_i.2.ackq~sq~lq~t rd_i.3.ackq~ sq~lq~t wrt_i.3.ackq~sq~lsq~ q~q~zq~toutputq~ sq~lq~t write.1.reqq~9sq~lq~t write.2.reqq~ wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell Cell1_Cell2 = INTER(Cell1, Cell2) Inst_Cell1 = <(rd,rd_i.1),(wrt,wrt_i.1)> Cell1 = rename(Cell, Inst_Cell1) Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> Cell2 = rename(Cell, Inst_Cell2) Cell1_Cell2_INTER_Cell3 = INTER(Cell1_Cell2_INTER, Cell3) Inst_Cell1_Cell2_INTER = <(rd,rd_i.1),(wrt,wrt_i.1),(rd,rd_i.2),(wrt,wrt_i.2)> Cell1_Cell2_INTER = rename(Cell1_Cell2, Inst_Cell1_Cell2_INTER) Inst_Cell3 = <(rd,rd_i.3),(wrt,wrt_i.3)> Cell3 = rename(Cell, Inst_Cell3) maxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) Cell1_Cell2_INTER_Cell3_INTER_Controller3 = COMM(Cell1_Cell2_INTER_Cell3_INTER, Controller3,wrt_i.1,write.1) Inst_Cell1_Cell2_INTER_Cell3_INTER = <(rd,rd_i.1),(wrt,wrt_i.1),(rd,rd_i.2),(wrt,wrt_i.2),(rd,rd_i.3),(wrt,wrt_i.3)> Cell1_Cell2_INTER_Cell3_INTER = rename(Cell1_Cell2_INTER_Cell3, Inst_Cell1_Cell2_INTER_Cell3_INTER) Inst_Controller3 = <(write,write),(read,read),(input,input),(output,output)> Controller3 = rename(Controller, Inst_Controller3) sq~w q~q~q~q~q~q~q~q~q~q~xsq~wxsq~wxt)Cell1_Cell2_INTER_Cell3_INTER_Controller3sq~wxsq~wxsq~wxsq~Rtsq~wq~gq~iq~kq~mq~oq~qxsq~wxsq~wq~}q~q~q~q~q~xtCell1_Cell2_INTER_Cell3_INTERsq~wq~q~q~q~q~q~xq~sq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell Cell1_Cell2 = INTER(Cell1, Cell2) Inst_Cell1 = <(rd,rd_i.1),(wrt,wrt_i.1)> Cell1 = rename(Cell, Inst_Cell1) Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> Cell2 = rename(Cell, Inst_Cell2) Cell1_Cell2_INTER_Cell3 = INTER(Cell1_Cell2_INTER, Cell3) Inst_Cell1_Cell2_INTER = <(rd,rd_i.1),(wrt,wrt_i.1),(rd,rd_i.2),(wrt,wrt_i.2)> Cell1_Cell2_INTER = rename(Cell1_Cell2, Inst_Cell1_Cell2_INTER) Inst_Cell3 = <(rd,rd_i.3),(wrt,wrt_i.3)> Cell3 = rename(Cell, Inst_Cell3) sq~wq~q~q~q~q~q~xsq~wxsq~wxtCell1_Cell2_INTER_Cell3sq~wxsq~wxsq~wxsq~Rq~sq~wq~gq~iq~kq~mxsq~wxsq~wq~}q~q~q~xtCell1_Cell2_INTERsq~wq~q~q~q~xq~sq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell Cell1_Cell2 = INTER(Cell1, Cell2) Inst_Cell1 = <(rd,rd_i.1),(wrt,wrt_i.1)> Cell1 = rename(Cell, Inst_Cell1) Inst_Cell2 = <(rd,rd_i.2),(wrt,wrt_i.2)> Cell2 = rename(Cell, Inst_Cell2) sq~wq~q~q~q~xsq~wxsq~wxt Cell1_Cell2sq~wxsq~wxsq~wxsq~q~sq~wq~gq~ixsq~wxsq~wq~}q~xtCell1sq~wq~q~xq~q~q~sq~q~sq~wq~kq~mxsq~wxsq~wq~q~xtCell2sq~wq~q~xsq~wq~q~xq~q~sq~q~sq~wq~oq~qxsq~wxsq~wq~q~xtCell3sq~wq~q~xsq~wq~q~xq~q~sq~q~sq~wq~sq~uq~wq~yxsq~wxsq~wq~q~q~q~q~q~q~xt Controller3sq~wq~q~q~q~q~q~q~xsq~wq~q~q~q~q~q~xq~bq~xt PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e)sq~wq~q~q~xsq~t COntrollersq~sq~wsq~ tcctrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~Dxsq~tValuet intervaloxsq~ q~;twrtsq~wq~>q~Gxsq~ q~;twritesq~wsq~tCellIdq~Iq~>q~Gxsq~ q~;treadsq~wq~Pq~>q~Gxsq~ tintinputsq~wq~Gxsq~ touttoutputsq~wq~Gxsq~ ptwrt_isq~wq~Pq~>q~Gxsq~ ptrd_isq~wq~Pq~>q~Gxxsq~wsq~ft@Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cellsq~wq~:q~Jxsq~wxsq~wsq~lq~:trd.reqt.reqsq~lq~Jtwrt.reqt.reqxtCellsq~wsq~lq~:trd.ackt.acksq~lq~Jtwrt.ackt.ackxsq~wsq~trdq~:tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~JtDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1) sq~wq~Mq~Rq~Uq~Yxsq~wxsq~wsq~lq~Utinputtsq~lq~Mt write.1.ackt.1.acksq~lq~Mt write.2.ackt.2.acksq~lq~Mt write.3.ackt.3.acksq~lq~Rt read.1.ackt.1.acksq~lq~Rt read.2.ackt.2.acksq~lq~Rt read.3.ackt.3.ackxt Controllersq~wsq~lq~Ytoutputq~sq~lq~Mt write.1.reqt.1.reqsq~lq~Mt write.2.reqt.2.reqsq~lq~Mt write.3.reqt.3.reqsq~lq~Rt read.1.reqt.1.reqsq~lq~Rt read.2.reqt.2.reqsq~lq~Rt read.3.reqt.3.reqxsq~wsq~twrite.1q~MtDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~MtDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~MtDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~RtDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~RtDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~RtDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wsq~Rtsq~wsq~ ptrd_i.1q~=sq~ ptwrt_i.1q~Lsq~ ptrd_i.2q~=sq~ ptwrt_i.2q~Lsq~ ptrd_i.3q~=sq~ ptwrt_i.3q~Lxsq~wxsq~wsq~lsq~ q~;q~q~=t rd_i.1.reqq~ksq~lsq~ q~;q~q~Lt wrt_i.1.reqq~nsq~lsq~ q~;q~q~=t rd_i.2.reqq~ksq~lsq~ q~;q~q~Lt wrt_i.2.reqq~nsq~lsq~ q~;q~q~=t rd_i.3.reqq~ksq~lsq~ q~;q~q~Lt wrt_i.3.reqq~nxtC1_C2_INTER_C3_INTERsq~wsq~lq~t rd_i.1.ackq~ssq~lq~t wrt_i.1.ackq~vsq~lq~t rd_i.2.ackq~ssq~lq~t wrt_i.2.ackq~vsq~lq~t rd_i.3.ackq~ssq~lq~t wrt_i.3.ackq~vxsq~wsq~trd_i.1q~tDUAL_PROT_CELL(rd_i.1)tPROT_CELL(rd_i.1)sq~twrt_i.1q~tDUAL_PROT_CELL(wrt_i.1)tPROT_CELL(wrt_i.1)sq~trd_i.2q~tDUAL_PROT_CELL(rd_i.2)tPROT_CELL(rd_i.2)sq~twrt_i.2q~tDUAL_PROT_CELL(wrt_i.2)tPROT_CELL(wrt_i.2)sq~trd_i.3q~tDUAL_PROT_CELL(rd_i.3)tPROT_CELL(rd_i.3)sq~twrt_i.3q~tDUAL_PROT_CELL(wrt_i.3)tPROT_CELL(wrt_i.3)xsq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell C1_C2 = INTER(C1, C2) Inst_C1 = <(rd,rd_i.1),(wrt,wrt_i.1)> C1 = rename(Cell, Inst_C1) Inst_C2 = <(rd,rd_i.2),(wrt,wrt_i.2)> C2 = rename(Cell, Inst_C2) C1_C2_INTER_C3 = INTER(C1_C2_INTER, C3) Inst_C1_C2_INTER = <(rd,rd_i.1),(wrt,wrt_i.1),(rd,rd_i.2),(wrt,wrt_i.2)> C1_C2_INTER = rename(C1_C2, Inst_C1_C2_INTER) Inst_C3 = <(rd,rd_i.3),(wrt,wrt_i.3)> C3 = rename(Cell, Inst_C3) sq~wq~:q~Jq~:q~Jq~:q~Jxsq~wxsq~wxtC1_C2_INTER_C3sq~wxsq~wxsq~wxsq~Rq~sq~wq~q~q~q~xsq~wxsq~wq~q~q~q~xt C1_C2_INTERsq~wq~q~q~q~xsq~wq~q~q~q~ xsq~wxsq~ftCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell C1_C2 = INTER(C1, C2) Inst_C1 = <(rd,rd_i.1),(wrt,wrt_i.1)> C1 = rename(Cell, Inst_C1) Inst_C2 = <(rd,rd_i.2),(wrt,wrt_i.2)> C2 = rename(Cell, Inst_C2) sq~wq~:q~Jq~:q~Jxsq~wxsq~wxtC1_C2sq~wxsq~wxsq~wxsq~q~esq~wq~q~xsq~wxsq~wq~q~xtC1sq~wq~q~xsq~wq~q~xq~q~dsq~q~esq~wq~q~xsq~wxsq~wq~q~xtC2sq~wq~q~xsq~wq~q~ xq~q~dsq~q~esq~wq~q~xsq~wxsq~wq~q~xtC3sq~wq~q~xsq~wq~q~xq~q~dsq~q~sq~wsq~ ptwriteq~Osq~ ptreadq~Tsq~ ptinputq~Xsq~ ptoutputq~\xsq~wxsq~wsq~lsq~ q~Vq~Mq~Xtinputq~sq~lsq~ q~;q~Iq~Ot write.1.ackq~sq~lq~Vt write.2.ackq~sq~lq~Vt write.3.ackq~sq~lsq~ q~;q~Kq~Tt read.1.ackq~sq~lq~]t read.2.ackq~sq~lq~]t read.3.ackq~xtContrsq~wsq~lsq~ q~Zq~Oq~\toutputq~sq~lq~Vt write.1.reqq~sq~lq~Vt write.2.reqq~sq~lq~Vt write.3.reqq~sq~lq~]t read.1.reqq~sq~lq~]t read.2.reqq~sq~lq~]t read.3.reqq~xsq~wsq~twrite.1q~HtDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~HtDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~HtDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~JtDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~JtDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~JtDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xq~q~xt PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e)sq~wq~>q~Gq~Pxsq~tCanaissq~sq~wsq~ ptrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ ptwrtsq~wq~q~xsq~ ptwritesq~wsq~tCellIdq~q~q~xsq~ ptreadsq~wq~q~q~xsq~ ptinputsq~wq~xsq~ ptoutputsq~wq~xsq~ ptwrt_isq~wq~q~q~xsq~ ptrd_isq~wq~q~q~xxsq~wxsq~wxq~sq~wq~q~q~xsq~t contract_cellsq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~xsq~ ptwritesq~wsq~tCellIdq~q~q~xsq~ ptreadsq~wq~q~q~xsq~ ptinputsq~wq~xsq~ ptoutputsq~wq~xsq~ ptwrt_isq~wq~q~q~xsq~ ptrd_isq~wq~q~q~xxsq~wsq~ftCell = let CellState(val) = rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x) within CellState(0)sq~wq~q~xsq~wsq~lq~trdtsq~lq~twrtq~xsq~wsq~lq~trd.reqt.reqsq~lq~twrt.reqt.reqxtCellsq~wsq~lq~trd.ackt.acksq~lq~twrt.ackt.ackxsq~wsq~trdq~tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxxsq~wxt!PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e) sq~wq~q~q~xsq~tcontract_Controllersq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~xsq~ q~twritesq~wsq~tCellIdq~ q~q~xsq~ q~treadsq~wq~'q~q~xsq~ q~tinputsq~wq~xsq~ touttoutputsq~wq~xsq~ ptwrt_isq~wq~'q~q~xsq~ ptrd_isq~wq~'q~q~xxsq~wsq~ftCell = let CellState(val) = rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x) within CellState(0)sq~wq~q~!xsq~wsq~lq~trdtsq~lq~!twrtq~@xsq~wsq~lq~trd.reqt.reqsq~lq~!twrt.reqt.reqxtCellsq~wsq~lq~trd.ackt.acksq~lq~!twrt.ackt.ackxsq~wsq~trdq~tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~!tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1)sq~wq~,q~/q~$q~)xsq~wsq~lq~,tinputq~@sq~lq~/toutputq~@sq~lq~$t write.1.ackt.1.acksq~lq~$t write.2.ackt.2.acksq~lq~$t write.3.ackt.3.acksq~lq~)t read.1.ackt.1.acksq~lq~)t read.2.ackt.2.acksq~lq~)t read.3.ackt.3.acksq~lq~$t write.1.reqt.1.reqsq~lq~$t write.2.reqt.2.reqsq~lq~$t write.3.reqt.3.reqsq~lq~)t read.1.reqt.1.reqsq~lq~)t read.2.reqt.2.reqsq~lq~)t read.3.reqt.3.reqsq~lq~$twrite.1t.1sq~lq~$twrite.2t.2sq~lq~$twrite.3t.3sq~lq~)tread.1t.1sq~lq~)tread.2t.2sq~lq~)tread.3t.3xsq~wq~`q~dq~gq~jq~mq~pq~sxt Controllersq~wq~bq~vq~yq~|q~q~q~xsq~wsq~twrite.1q~$tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~$tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~$tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~)tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~)tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~)tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wxt!PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e) sq~wq~q~q~'xsq~t Instanciasq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~xsq~ q~twritesq~wsq~tCellIdq~q~q~xsq~ q~treadsq~wq~q~q~xsq~ q~tinputsq~wq~xsq~ touttoutputsq~wq~xsq~ ptwrt_isq~wq~q~q~xsq~ ptrd_isq~wq~q~q~xxsq~wsq~ftCell = let CellState(val) = rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x) within CellState(0)sq~wq~q~xsq~wsq~lq~trdtsq~lq~twrtq~xsq~wsq~lq~trd.reqt.reqsq~lq~twrt.reqt.reqxtCellsq~wsq~lq~trd.ackt.acksq~lq~twrt.ackt.ackxsq~wsq~trdq~tDUAL_PROT_CELL(rd)t PROT_CELL(rd)sq~twrtq~tDUAL_PROT_CELL(wrt)tPROT_CELL(wrt)xsq~wxsq~ftmaxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1)sq~wq~q~q~q~xsq~wsq~lq~tinputq~sq~lq~toutputq~sq~lq~t write.1.ackt.1.acksq~lq~t write.2.ackt.2.acksq~lq~t write.3.ackt.3.acksq~lq~t read.1.ackt.1.acksq~lq~t read.2.ackt.2.acksq~lq~t read.3.ackt.3.acksq~lq~t write.1.reqt.1.reqsq~lq~t write.2.reqt.2.reqsq~lq~t write.3.reqt.3.reqsq~lq~t read.1.reqt.1.reqsq~lq~t read.2.reqt.2.reqsq~lq~t read.3.reqt.3.reqsq~lq~twrite.1t.1sq~lq~twrite.2t.2sq~lq~twrite.3t.3sq~lq~tread.1t.1sq~lq~tread.2t.2sq~lq~tread.3t.3xsq~wq~ q~q~q~q~q~q~ xt Controllersq~wq~q~#q~&q~)q~,q~/q~2xsq~wsq~twrite.1q~tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xsq~wxxsq~wsq~q~sq~wsq~ ptrd_i.1q~sq~ ptwrt_i.1q~xsq~wxsq~wsq~lsq~ q~q~hq~t rd_i.1.reqq~sq~lsq~ q~q~jq~t wrt_i.1.reqq~xtCell1sq~wsq~lq~nt rd_i.1.ackq~sq~lq~qt wrt_i.1.ackq~xsq~wsq~trd_i.1q~gtDUAL_PROT_CELL(rd_i.1)tPROT_CELL(rd_i.1)sq~twrt_i.1q~itDUAL_PROT_CELL(wrt_i.1)tPROT_CELL(wrt_i.1)xq~q~sq~q~sq~wsq~ ptrd_i.2q~sq~ ptwrt_i.2q~xsq~wxsq~wsq~lsq~ q~q~q~t rd_i.2.reqq~sq~lsq~ q~q~q~t wrt_i.2.reqq~xtCell2sq~wsq~lq~t rd_i.2.ackq~sq~lq~t wrt_i.2.ackq~xsq~wsq~trd_i.2q~tDUAL_PROT_CELL(rd_i.2)tPROT_CELL(rd_i.2)sq~twrt_i.2q~tDUAL_PROT_CELL(wrt_i.2)tPROT_CELL(wrt_i.2)xq~q~sq~q~sq~wsq~ ptrd_i.3q~sq~ ptwrt_i.3q~xsq~wxsq~wsq~lsq~ q~q~q~t rd_i.3.reqq~sq~lsq~ q~q~q~t wrt_i.3.reqq~xtCell3sq~wsq~lq~t rd_i.3.ackq~sq~lq~t wrt_i.3.ackq~xsq~wsq~trd_i.3q~tDUAL_PROT_CELL(rd_i.3)tPROT_CELL(rd_i.3)sq~twrt_i.3q~tDUAL_PROT_CELL(wrt_i.3)tPROT_CELL(wrt_i.3)xq~q~sq~q~ sq~wsq~ ptinputq~sq~ ptoutputq~sq~ ptwriteq~sq~ ptreadq~xsq~wxsq~wsq~lsq~ q~q~q~tinputq~sq~lsq~ q~q~q~t write.1.ackq~sq~lq~t write.2.ackq~sq~lq~t write.3.ackq~sq~lsq~ q~q~q~t read.1.ackq~sq~lq~t read.2.ackq~sq~lq~t read.3.ackq~"xt Controllerrsq~wsq~lsq~ q~q~q~toutputq~sq~lq~t write.1.reqq~%sq~lq~t write.2.reqq~(sq~lq~t write.3.reqq~+sq~lq~t read.1.reqq~.sq~lq~t read.2.reqq~1sq~lq~t read.3.reqq~4xsq~wsq~twrite.1q~tDUAL_PROT_CTRL(write.1)tPROT_CTRL(write.1)sq~twrite.2q~tDUAL_PROT_CTRL(write.2)tPROT_CTRL(write.2)sq~twrite.3q~tDUAL_PROT_CTRL(write.3)tPROT_CTRL(write.3)sq~tread.1q~tDUAL_PROT_CTRL(read.1)tPROT_CTRL(read.1)sq~tread.2q~tDUAL_PROT_CTRL(read.2)tPROT_CTRL(read.2)sq~tread.3q~tDUAL_PROT_CTRL(read.3)tPROT_CTRL(read.3)xq~cq~ xt!PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e) sq~wq~q~q~xx