¬íysrjava.util.LinkedList )S]J`ˆ"xpwsrLOGIC.ObjectSaved^¬Ï‚×tLnometLjava/lang/String;LsavetLLOGIC/ObjectList;xptcanaissrLOGIC.ObjectList¢Õª7 ³žIdefaultrenameNumberL channelListtLjava/util/List;L contractListq~L instanceListq~LprocessosAuxiliaresq~LtypeListq~xpsq~wsr LOGIC.Channel‡p^9MÙ0FLflagq~Lnameq~Ltypeq~xpptrdsq~wsrLOGIC.Datatype¼ 4ª3ÇLdatatypeq~xr LOGIC.Type [ÍKÖàÀLnomeq~Ltipoq~xpt Directiontdatatypesq~wsrLOGIC.DatatypeElementEoЯŸ èÚLnameq~Ltypeq~xptreqtsq~tackq~xsrLOGIC.IntervalType—Ve¹ImaxImimxq~tValuet intervaloxsq~ ptwrtsq~wq~q~xxsq~wxsq~wxq~sq~wq~q~xsq~tcontractsq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~3xsq~tValuet intervaloxsq~ q~*twrtsq~wq~-q~6xxsq~wsrLOGIC.Contract±é"~ d¡O ZflagLbehaviorq~Lchannelq~Leventsq~Linq~Lnameq~Loutq~L protocolostLjava/util/LinkedList;Ltypeq~xptPBricRingCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> BricRingCellsq~wq~)q~9xsq~wsrLOGIC.EventChannel wÇ¢?ËäLchanneltLLOGIC/Channel;Leventoq~Lsufixoq~xpq~)trd.reqt.reqsq~Cq~9twrt.reqt.reqsq~Cq~)trd.reqt.reqsq~Cq~)trd.ackt.acksq~Cq~9twrt.ackt.ackxsq~wq~Eq~Hxt BricRingCellsq~wq~Nq~Qxsq~wxsq~wxxsq~wxtsq~wq~-q~6xsq~tcontract_channelsq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~jxsq~tValuet intervaloxsq~ q~atwrtsq~wq~dq~mxsq~ ptwritesq~wsq~tCellIdt intervaloq~dq~mxsq~ ptreadsq~wq~vq~dq~mxsq~ ptinputsq~wq~mxsq~ ptoutputsq~wq~mxxsq~wsq~=tPBricRingCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> BricRingCellsq~wq~`q~pxsq~wsq~Cq~`trd.reqt.reqsq~Cq~ptwrt.reqt.reqsq~Cq~`trd.reqt.reqsq~Cq~`trd.ackt.acksq~Cq~ptwrt.ackt.ackxsq~wq~‡q~Šxt BricRingCellsq~wq~q~“xsq~wxsq~wxxsq~wxtsq~wq~dq~mq~vxsq~tcontract_controlersq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~¬xsq~tValuet intervaloxsq~ q~£twrtsq~wq~¦q~¯xsq~ tintwritesq~wsq~tCellIdt intervaloq~¦q~¯xsq~ q~¶treadsq~wq~¹q~¦q~¯xsq~ q~¶tinputsq~wq~¯xsq~ touttoutputsq~wq~¯xxsq~wsq~=tPBricRingCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> BricRingCellsq~wq~¢q~²xsq~wsq~Cq~¢trd.reqt.reqsq~Cq~²twrt.reqt.reqsq~Cq~¢trd.reqt.reqsq~Cq~¢trd.ackt.acksq~Cq~²twrt.ackt.ackxsq~wq~Ëq~Îxt BricRingCellsq~wq~Ôq~×xsq~wxsq~wxsq~=t¨maxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1)sq~wq~¿q~Âq~µq~¼xsq~wsq~Cq~¿tinputtsq~Cq~Âtoutputq~åsq~Cq~µt write.1.ackt.1.acksq~Cq~¼t read.1.reqt.1.reqsq~Cq~µt write.2.ackt.2.acksq~Cq~µt write.3.ackt.3.acksq~Cq~¼t read.1.ackt.1.acksq~Cq~¼t read.2.ackt.2.acksq~Cq~¼t read.3.ackt.3.acksq~Cq~µt write.1.reqt.1.reqsq~Cq~µt write.2.reqt.2.reqsq~Cq~µt write.3.reqt.3.reqsq~Cq~¼t read.1.reqt.1.reqsq~Cq~¼t read.2.reqt.2.reqsq~Cq~¼t read.3.reqt.3.reqxsq~wq~ãq~èq~îq~ñq~ôq~÷q~úxt Controllersq~wq~æq~ýq~q~q~q~ q~ xsq~wxsq~wxxsq~wxq~åsq~wq~¦q~¯q~¹xsq~tcontrato_controlersq~sq~wsq~ tintrdsq~wsq~t Directiontdatatypesq~wsq~treqtsq~tackq~$xsq~tValuet intervaloxsq~ q~twrtsq~wq~q~'xsq~ tintwritesq~wsq~tCellIdt intervaloq~q~'xsq~ q~.treadsq~wq~1q~q~'xsq~ q~.tinputsq~wq~'xsq~ touttoutputsq~wq~'xsq~ ptrd_isq~wq~1q~q~'xsq~ ptwrt_isq~wq~1q~q~'xxsq~wsq~=tPBricRingCell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> BricRingCellsq~wq~q~*xsq~wsq~Cq~trd.reqt.reqsq~Cq~*twrt.reqt.reqsq~Cq~trd.reqt.reqsq~Cq~trd.ackt.acksq~Cq~*twrt.ackt.ackxsq~wq~Iq~Lxt BricRingCellsq~wq~Rq~Uxsq~wxsq~wxsq~=t¨maxbuff = 4 maxring = maxbuff - 1 Controller = let ControllerState(cache,size,top,bot) = InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot) InputController(cache,size,top,bot) = size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot) [] size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot)) OutputController(cache,size,top,bot) = size > 0 & output!cache -> (size > 1 & -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive -- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1) (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)) [] size == 1 & ControllerState(cache,0,top,bot)) within -- The initial value of the cache is irrelevant, since the size is 0. ControllerState(0,0,1,1)sq~wq~7q~:q~-q~4xsq~wsq~Cq~7tinputtsq~Cq~:toutputq~csq~Cq~-t write.1.ackt.1.acksq~Cq~4t read.1.reqt.1.reqsq~Cq~-t write.2.ackt.2.acksq~Cq~-t write.3.ackt.3.acksq~Cq~4t read.1.ackt.1.acksq~Cq~4t read.2.ackt.2.acksq~Cq~4t read.3.ackt.3.acksq~Cq~-t write.1.reqt.1.reqsq~Cq~-t write.2.reqt.2.reqsq~Cq~-t write.3.reqt.3.reqsq~Cq~4t read.1.reqt.1.reqsq~Cq~4t read.2.reqt.2.reqsq~Cq~4t read.3.reqt.3.reqxsq~wq~aq~fq~lq~oq~rq~uq~xxt Controllersq~wq~dq~{q~~q~q~„q~‡q~Šxsq~wxsq~wxxsq~wxt!PROT_CELL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> PROT_CELL(e) DUAL_PROT_CELL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> DUAL_PROT_CELL(e) PROT_CTRL(e) = |~| v1:Value @ e.req.v1 -> e.ack?v2 -> PROT_CTRL(e) DUAL_PROT_CTRL(e) = |~| v2:Value @ e.req?v1 -> e.ack.v2 -> DUAL_PROT_CTRL(e) sq~wq~q~'q~1xx