Checking fdrLog/BUF1.csp

Checking Test(inter(inputs(BUF1),outputs(BUF1)) == {}) [T= ERROR
xtrue
BEGIN TRACE example=0 process=1
error
END TRACE example=0 process=1

Checking HideAll(BUF1) :[divergence free [FD]]
xtrue
BEGIN TRACE example=0 process=0

END TRACE example=0 process=0

Checking BUF1 :[divergence free [FD]]
true

Checking LHS_InputDet(BUF1) [F= RHS_InputDet(BUF1)
true

Checking LHS_OutputDec_A(BUF1) [F= RHS_OutputDec_A(BUF1)
true

Checking LHS_OutputDec_B(BUF1,write1) [F= RHS_OutputDec_B(BUF1,write1)
true

Checking LHS_OutputDec_B(BUF1,read1) [F= RHS_OutputDec_B(BUF1,read1)
true