include "sequence_aux.csp" 
include "function_aux.csp" 
include "auxiliar.csp" 
include "rules.csp"


datatype Direction = req | ack
Value = {1..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel rd_i : CellId.Direction.Value
channel wrt_i : CellId.Direction.Value


Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell




Inst_Cell0 = <(rd,rd_i.1),(wrt,wrt_i.1)> 
Cell0 = rename(Cell, Inst_Cell0) 

Inst_Cell1 = <(rd,rd_i.2),(wrt,wrt_i.2)> 
Cell1 = rename(Cell, Inst_Cell1) 


GET_CHANNELS(P) =
 	 let f =
 	 < 
	(Cell0, { rd_i.1,wrt_i.1 }),

	(Cell1, { rd_i.2,wrt_i.2 })

 	 > 

 	 within apply(f,P )

inputs( P ) = 
 	 let f = 
	<
 	 ( Cell0, {| rd_i.1.req,wrt_i.1.req |}),
 	 ( Cell1, {| rd_i.2.req,wrt_i.2.req |})
 	 > 

 	 within apply(f, P )
 outputs( P ) = 
 	 let f =
	  < 
	 ( Cell0, {| rd_i.1.ack,wrt_i.1.ack |}),
	 ( Cell1, {| rd_i.2.ack,wrt_i.2.ack |})
 	 >
 	 within apply(f, P )

--INTERLEAVING COMPOSITION 
Cell0_Cell1 = INTER(Cell0,Cell1) 
assert STOP [T= RUN(inter(events(Cell0),events(Cell1)))
assert Cell0_Cell1:[deadlock free[FD]]