Madiel de Souza Conserva Filho / bts

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BRIC/fdrLog/Controller_saida_1.386882738396E12.log 850 Bytes
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eeb5cac08   Madiel de Souza Conserva Filho   first 
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  Checking cspFiles/Controller.csp
  
  Checking Test(inter(inputs(Controller),outputs(Controller)) == {}) [T= ERROR
  xtrue
  BEGIN TRACE example=0 process=1
  error
  END TRACE example=0 process=1
  
  Checking HideAll(Controller) :[divergence free [FD]]
  xtrue
  BEGIN TRACE example=0 process=0
  
  END TRACE example=0 process=0
  
  Checking Controller :[divergence free [FD]]
  true
  
  Checking LHS_InputDet(Controller) [F= RHS_InputDet(Controller)
  true
  
  Checking LHS_OutputDec_A(Controller) [F= RHS_OutputDec_A(Controller)
  true
  
  Checking LHS_OutputDec_B(Controller,input) [F= RHS_OutputDec_B(Controller,input)
  true
  
  Checking LHS_OutputDec_B(Controller,output) [F= RHS_OutputDec_B(Controller,output)
  true
  
  Checking LHS_OutputDec_B(Controller,write) [F= RHS_OutputDec_B(Controller,write)
  true
  
  Checking LHS_OutputDec_B(Controller,read) [F= RHS_OutputDec_B(Controller,read)
  true