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BRIC/cspFiles/Controllerr.csp
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include "sequence_aux.csp"
include "function_aux.csp"
include "auxiliar.csp"
include "rules.csp"
datatype Direction = req | ack
Value = {0..3}
CellId = {0..3}
channel rd : Direction.Value
channel wrt : Direction.Value
channel write : CellId.Direction.Value
channel read : CellId.Direction.Value
channel input : Value
channel output : Value
channel wrt_i : CellId.Direction.Value
channel rd_i : CellId.Direction.Value
Cell =
let CellState(val) =
rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x)
within
CellState(0)
maxbuff = 4
maxring = maxbuff - 1
Controller =
let ControllerState(cache,size,top,bot) =
InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot)
InputController(cache,size,top,bot) =
size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot)
[]
size > 0 & write.top.req!x -> write.top.ack?dumb -> ControllerState(cache,size+1,(top%maxring)+1,bot))
OutputController(cache,size,top,bot) =
size > 0 & output!cache -> (size > 1 &
-- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive
-- read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)
(|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1))
[]
size == 1 & ControllerState(cache,0,top,bot))
within
-- The initial value of the cache is irrelevant, since the size is 0.
ControllerState(0,0,1,1)
RenameContract(i) = Controller [[input <- input,output <- output,write <- write,read <- read]]
Inst_Controllerr = <(input,input),(output,output),(write,write),(read,read)>
Controllerr = rename(Controller, Inst_Controllerr)
GET_CHANNELS(P) =
let f =
<
(Controllerr, {
input,output,write,read })
>
within apply(f,P )
inputs(P) =
let f =
<
( Controllerr, {| input, write.1.ack, write.2.ack, write.3.ack, read.1.ack, read.2.ack, read.3.ack |})
>
within apply(f, P )
outputs(P) =
let f =
<
( Controllerr, {| output, write.1.req, write.2.req, write.3.req, read.1.req, read.2.req, read.3.req |})
>
within apply(f,P)
--Condition A.1: Alphabets are disjont
--assert STOP [T= RUN(inter(events(Controllerr),events(Controllerr)))
--Condition A.2: I/O Process
--Condition A.2.1: Every channel in P is an I/O Channel
assert not Test(inter(inputs(Controllerr),outputs(Controllerr)) == {}) [T= ERROR
--Condition A.2.2: The contract has infinite set of traces
assert not HideAll(Controllerr):[divergence free [FD]]
--Condition A.2.3: The contract is divergence-free
assert Controllerr:[divergence free [FD]]
--Condition A.2.4: The contract is input deterministic
assert LHS_InputDet(Controllerr) [F= RHS_InputDet(Controllerr)
--Condition A.2.5: The contract is strong output decisive
assert LHS_OutputDec_A(Controllerr) [F= RHS_OutputDec_A(Controllerr)
assert LHS_OutputDec_B(Controllerr,input) [F= RHS_OutputDec_B(Controllerr,input)
assert LHS_OutputDec_B(Controllerr,output) [F= RHS_OutputDec_B(Controllerr,output)
assert LHS_OutputDec_B(Controllerr,write) [F= RHS_OutputDec_B(Controllerr,write)
assert LHS_OutputDec_B(Controllerr,read) [F= RHS_OutputDec_B(Controllerr,read)
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