Madiel de Souza Conserva Filho / bts

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BRIC/cspFiles/Cell0.csp~ 2.87 KB
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eeb5cac08   Madiel de Souza Conserva Filho   first 
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  include "sequence_aux.csp" 
  include "function_aux.csp" 
  include "auxiliar.csp" 
  include "rules.csp"
  
  
  datatype Direction = req | ack
  Value = {1..3}
  CellId = {0..3}
  channel rd : Direction.Value
  channel wrt : Direction.Value
  channel write : CellId.Direction.Value
  channel read : CellId.Direction.Value
  channel input : Value
  channel output : Value
  channel rd_i : CellId.Direction.Value
  channel wrt_i : CellId.Direction.Value
  
  
  Cell = wrt.req?x -> wrt.ack.x -> rd.req?dumb -> rd.ack!x -> Cell
  maxbuff = 4
  
  maxring = maxbuff - 1
  
  Controller =
   let ControllerState(cache,size,top,bot) =
         InputController(cache,size,top,bot) [] OutputController(cache,size,top,bot)
  
       InputController(cache,size,top,bot) =
         size < maxbuff & input?x -> (size == 0 & ControllerState(x,1,top,bot)
                                      []
                                      size > 0 & write.top.req!x -> write.top.ack?dumb ->  ControllerState(cache,size+1,(top%maxring)+1,bot))
  
       OutputController(cache,size,top,bot) =
         size > 0 & output!cache -> (size > 1 &
  -- A requisição de leitura não ser uma "escolha externa (via input on dumb)" para que o processo seja Strong Output Decisive
  --                                        read.bot.req?dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1)
                                          (|~| dumb:Value @ read.bot.req.dumb -> read.bot.ack?x -> ControllerState(x,size-1,top,(bot%maxring)+1))
                                     []
                                     size == 1 & ControllerState(cache,0,top,bot))
  
   within
   --  The initial value of the cache is irrelevant, since the size is 0.
     ControllerState(0,0,1,1)
  
  
  
  RenameContract(i) = Cell [[rd <- rd_i.1,wrt <- wrt_i.1]] 
  Inst_Cell0 = <(rd,rd_i.1),(wrt,wrt_i.1)> 
  Cell0 = rename(Cell, Inst_Cell0) 
  
  
  GET_CHANNELS(P) =
   	 let f =
   	 < 
   	 (Cell0, { 
  rd_i.1,wrt_i.1 }) 
   	 > 
  
   	 within apply(f,P )
  
  inputs(P) = 
   	 let f = 
  
   	 < 
   ( Cell0, {| rd_i.1.req, wrt_i.1.req |}) 
   	 > 
  
   	 within apply(f, P )
  
  outputs(P) = 
   	 let f =
   	 < 
   ( Cell0, {| rd_i.1.ack, wrt_i.1.ack |}) 
   	 >
   	 within apply(f,P)
  
  --Condition A.1: Alphabets are disjont
  --assert STOP [T= RUN(inter(events(Cell0),events(Cell0)))
  
  --Condition A.2: I/O Process
  --Condition A.2.1: Every channel in P is an I/O Channel
  assert not Test(inter(inputs(Cell0),outputs(Cell0)) == {}) [T= ERROR
  
  --Condition A.2.2: The contract has infinite set of traces
  assert not HideAll(Cell0):[divergence free [FD]]
  
  --Condition A.2.3: The contract is divergence-free
  assert Cell0:[divergence free [FD]]
  
  --Condition A.2.4: The contract is input deterministic
  assert LHS_InputDet(Cell0) [F= RHS_InputDet(Cell0)
  
  --Condition A.2.5: The contract is strong output decisive
  assert LHS_OutputDec_A(Cell0) [F= RHS_OutputDec_A(Cell0)
  assert LHS_OutputDec_B(Cell0,rd_i.1) [F= RHS_OutputDec_B(Cell0,rd_i.1)
  assert LHS_OutputDec_B(Cell0,wrt_i.1) [F= RHS_OutputDec_B(Cell0,wrt_i.1)