Blame view

BRIC/cspFiles/Cell.csp~ 1.73 KB
eeb5cac08   Madiel de Souza Conserva Filho   first
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
  include "sequence_aux.csp" 
  include "function_aux.csp" 
  include "auxiliar.csp" 
  include "rules.csp"
  
  datatype Direction = req | ack
  Value = {1..3}
  CellId = {0..3}
  channel rd : Direction.Value
  channel wrt : Direction.Value
  channel write : CellId.Direction.Value
  channel read : CellId.Direction.Value
  channel input : Value
  channel output : Value
  channel wrt_i : CellId.Direction.Value
  channel rd_i : CellId.Direction.Value
  
  ell = 
    let CellState(val) =
      rd.req?dumb -> rd.ack!val -> CellState(val) [] wrt.req?x -> wrt.ack.x -> CellState(x)
    within
      CellState(0)
  
  
  GET_CHANNELS(P) =
   	 let f =
   	 < 
   	(Cell, { wrt,rd,wrt_i,rd_i }) 
   	 > 
  
   	 within apply(f,P )
  
  inputs(P) = 
   	 let f = 
  
   	 < 
   	 ( Cell, {| wrt.req, rd.req |}) 
   	 > 
  
   	 within apply(f, P )
  
  outputs(P) = 
   	 let f =
   	 < 
   	 ( Cell, {| wrt.ack, rd.ack |}) 
   	 >
   	 within apply(f,P)
  
  --Condition A.1: Alphabets are disjont
  --assert STOP [T= RUN(inter(events(Cell),events(Cell)))
  
  --Condition A.2: I/O Process
  --Condition A.2.1: Every channel in P is an I/O Channel
  assert not Test(inter(inputs(Cell),outputs(Cell)) == {}) [T= ERROR
  
  --Condition A.2.2: The contract has infinite set of traces
  assert not HideAll(Cell):[divergence free [FD]]
  
  --Condition A.2.3: The contract is divergence-free
  assert Cell:[divergence free [FD]]
  
  --Condition A.2.4: The contract is input deterministic
  assert LHS_InputDet(Cell) [F= RHS_InputDet(Cell)
  
  --Condition A.2.5: The contract is strong output decisive
  assert LHS_OutputDec_A(Cell) [F= RHS_OutputDec_A(Cell)
  assert LHS_OutputDec_B(Cell,wrt) [F= RHS_OutputDec_B(Cell,wrt)
  assert LHS_OutputDec_B(Cell,rd) [F= RHS_OutputDec_B(Cell,rd)
  assert LHS_OutputDec_B(Cell,wrt_i) [F= RHS_OutputDec_B(Cell,wrt_i)
  assert LHS_OutputDec_B(Cell,rd_i) [F= RHS_OutputDec_B(Cell,rd_i)